Static random access memory (SRAM) device based field programmable gate arrays (FPGAs) require that their internal configuration memory be loaded from an external source whenever power is applied to the FPGA. A common approach to provide data to the FPGA is the use of a serial configured electrically erasable programmable read only memory (EEPROM). A FPGA device contains circuitry which allows the FPGA at power-up to read the contents of the EEPROM and load this data into its own configuration memory.
Often it is desirable to change the contents of the serial-configuration EEPROM in order to update the functionality of the FPGA device in a system. Using traditional approaches, system operation must be suspended, power turned off, and the EEPROM physically removed from the system, reprogrammed and replaced. Newer methods allow in-system programming where the EEPROM is not removed from the system to be reprogrammed, but such systems typically require special hardware and interruption of normal system operation. Further, such methods may require the use of proprietary EEPROMs and non-standard interfaces to a printed wiring board.
A need has thus arisen for a method of reprogramming an EEPROM device which provides internal configuration memory for a FPGA without the requirement of special hardware, interruption of normal system operation during the reprogramming process, or special interfaces.